A desire for increased performance improvements, such as increased bandwidth, reduced latency, and lower power, among other improvements, is fostering an implementation of three-dimensional integrated circuit (3D-IC) designs. In a 3D-IC, silicon wafers and/or dies are stacked and interconnected vertically using through silicon vias (TSVs) to behave as a single device in order to achieve desired performance improvements. The TSVs enable communication between the dies in the 3D stack. However, the TSVs are limited in number and use valuable real-estate on the chip.